1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting integrated circuit product.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
For many early device technology generations, the gate structures of most transistor elements (planar and FinFET devices) were comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that include a so-called high-k dielectric gate insulation layer (k-value of approximately 10 or greater) and one or more metal layers that function as the gate electrode have been implemented. Such alternative gate structures—typically known as high-k/metal gate structures (HK/MG structures)—have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. Generally, the replacement gate process involves: forming a basic transistor structure (planar, FinFet, nanowire, etc.) with a sacrificial gate structure positioned between sidewall spacers; forming the source/drain regions for the device; performing the necessary anneal process to activate implanted dopant materials; removing the sacrificial gate structure so as to define a gate cavity for the replacement gate structure between the spacers; depositing a high-k gate insulation layer and a plurality of metal layers in the gate cavity; performing a CMP process to remove excess materials positioned outside of the gate cavity; recessing the gate materials within the gate cavity to make room for a gate cap layer; and forming a gate cap layer in the gate cavity above the recessed gate materials. FIG. 1A is a simplistic and enlarged depiction of an illustrative replacement gate structure 30 that is formed above a semiconductor substrate 12. Also depicted are sidewall spacers 16, a layer of insulating material 18 and a gate cap layer 31. As depicted, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A, a work-function adjusting metal layer 30B and other layers of metal 30C, 30D and 30E. The final stacks of materials in replacement gate structures are different for NFET devices and PFET devices, although they may share some of the same materials.
However, as the gate length of transistor devices has decreased, the physical size of the gate cavity has also decreased. Thus, it is becoming physically difficult to fit all of the layers of material needed for an HK/MG replacement gate structure within such reduced-size gate cavities, particularly for NMOS devices, due to the greater number of layers of material that are typically used to form the HK/MG structures for the NMOS devices as compared to PMOS devices. For example, as gate lengths continue to decrease, voids or seams may be formed as the various layers of material are deposited into the gate cavity. That is, as the layers of material are formed in the gate cavity, the remaining space within the gate cavity becomes very small. As the later metal layers are formed, the remaining space within the gate cavity may be only about 1-2 nm in width or even smaller. In some cases, there may be essentially no remaining space in the gate cavity. This may lead to so-called “pinch-off” of metal layers such that voids or seams may be formed in the overall replacement gate structure, which may result in devices that perform at levels less than anticipated or, in some cases, the formation of devices that are simply not acceptable and have to be discarded.
FIG. 1B depicts an illustrative situation where an N-type device 10N will be formed on an N-Active region 12A adjacent to a P-type device 10P that is formed on a P-Active region 12B. As depicted, the two devices 10N, 10P share a common gate structure. Such an arrangement is typically found in, for example, an SRAM product, a ring oscillator product, etc. The N-type device 10N is separated from the P-type device 10P by an illustrative shallow trench isolation region 14 that is formed in the substrate 12. In the depicted example, the common gate structure for both devices will be formed using a so-called “replacement gate” or “gate last” technique.
When forming replacement gate structures in CMOS applications (where both N- and P-type devices are formed on the same substrate), it is common to deposit the work function metal layer for one of the devices, e.g., the N-type device (NWF metal), into the gate cavities for both the N-type device 10N and the P-type device 10P at the same time, and later selectively remove the undesirable NWF metal layer from the P-type device 10P by masking the N-type device 10N and etching the NWF metal layer in the gate cavity for the P-type device 10P. The selective removal is accomplished by forming a patterned masking layer that exposes, in this example, the P-type device 10P, and thereafter performing an etching process to remove the exposed NWF metal layer from the P-type device 10P. Of course, the reverse could happen as well, i.e., the work function metal layer for the P-type device 10P (PWF metal) could be deposited in the gate cavities for both the N- and P-type devices 10N, 10P, and later selectively removed from the N-type device 10N. The selective removal of the undesired portions of the work function metal layer (N or P) from one of the devices occurs before the formation of additional layers of material within the replacement gate cavities.
As indicated above, it is becoming physically difficult to fit all of the layers of material needed for an HK/MG replacement gate structure within the reduced-size gate cavities found on advanced integrated circuit products. FIG. 1C depicts an example, wherein a replacement gate structure will be formed in a gate cavity 44. As depicted, a high-k gate insulation layer 40 was initially formed in the gate cavity 44. Thereafter, an illustrative work function metal layer 42 (N or P depending upon the device) was deposited into the gate cavity 44 above the high-k gate insulation layer 40. Additionally, FIG. 1C depicts the device after a recess etching process was performed on the work function metal layer 42 to remove some of the work function metal layer 42 from within the gate cavity 44. FIG. 1C depicts the situation where a void or opening 50 was created in the replacement gate structure as a result of the work function metal layer 42 “pinching-off” the gate cavity 44. FIG. 1D depicts a situation where, although the work function metal layer 42 did not “pinch-off” the gate cavity 44 when it was formed, the remaining space between portions of the work function metal layer 42 is so small that the masking layer 46, e.g., OPL, cannot fill the space between the portions of the work function metal layer 42, and thereby effectively creating a void 50 in the replacement gate structure at this point in the process flow.
In the case of forming replacement gate structures where opposite polarity devices share a common gate structure, the presence of such voids 50, whether created by the work function metal layer 42 pinching-off the gate cavity 44 (FIG. 1C) or due to the fact that the space between the portions of work function metal layer 42 cannot be filled by the masking layer 46 (FIG. 1D) is problematic. As noted above, to selectively remove unwanted work function metal from one of the devices, a masking layer, such as the masking layer 46, is formed to cover one of the devices and expose the other device so that the undesired work function metal may be removed from the exposed device. The removal of the work function metal layer is typically accomplished by performing a wet etching process. Thus, if voids or openings 50 are present in the portion of the replacement gate structure positioned above the isolation region 14 at the time the wet etching process is performed, the etchants can flow through the openings or voids 50 and attack the work function metal in the masked device. Such a situation can result in partial or substantially complete removal of the desired work function metal from the masked device which, in turn, can lead to substandard device performance and/or complete failure of the circuit that includes such a device.
The present disclosure is directed to novel methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting integrated circuit product that may solve or reduce one or more of the problems identified above.